A computer program comprises a series of program statements, also known as program instructions. Each program instruction accomplishes a specific task. The program instructions are binary machine instructions that the CPU can directly execute. The operating system loads the machine instructions into the main memory RAM to begin program execution.
Instruction Cycle
In the instruction cycle, the essential operation of the CPU is the time required to execute and fetch a complete instruction. Fetch, decode and execute cycle are the three steps that the CPU repetitively performs to complete one program instruction.
The instruction cycle comprises three main stages and is also addressed as the fetch-decode-execute cycle or fetch-execute cycle because of the steps involved.
They are as follows:
1. Fetch stage
2. Decode stage
3. Execute stage.
Steps Involved in Fetch Cycle
Fetch Cycle: The Program Counter contains the address of the instruction that has to be next executed at the start of the fetch cycle (PC).
Step 1: The address in the program counter is transferred to the memory address register (MAR), which is the only register connected to the address lines of the system bus.
Step 2: The MAR address is added to the address bus. The control unit then issues a READ command on the control bus, and the result is displayed on the data bus before being copied into the memory buffer register (MBR). The program counter is increased by one to prepare for the next instruction. ( These two actions can be performed concurrently to save time.)
Step 3: The MBR’s content is transferred to the instruction register (IR).
An essential Fetch Cycle also consists of four micro-operations, which can be represented symbolically as follows:
Here, a clock is available for timing purposes, and it emits clock pulses at regular intervals. Each micro-operation can be completed in the time of a single time unit. You can define a time unit by each clock pulse. As a result, all-time teams have the same duration.
Move the contents of the PC to MAR.
MAR-specified memory location contents are to be copied to the MBR. The process increases the PC’s content.
Copy the contents of the MBR to the IR.
Both the second and the third micro-operations occur during the second time unit.
Steps Involved in Instruction Fetch and Decode
Let’s take a look at the steps involved in the instruction cycle from the beginning to the end:
Step 1: Fetch Phase – The first phase of the instruction cycle
Here, the sequence counter (SC) is set to zero at the start of the instruction cycle.
SC – 0
Step 2: Fetch phase occurring at Clock Pulse (T-0)
Here, the instruction cycle stores the address of the next instruction in the program counter (PC) register. The PC’s content (address) is assigned to the address register in the first clock cycle (T-0) ( AR).
PC – AR
Step 3: Fetch phase occurring at Clock Pulse 1
In the next clock cycle (T-1), the instruction is read from memory and loaded into the instruction register (IR), while the program counter (PC) is also incremented by one. The program counter (PC) now points to the memory address of the next instruction to be retrieved.
PC – PC+1 AND IR -M [AR]
The Instruction Register (IR) is a 16-bit register capable of storing instructions in 16-bit format. The three components of the 16-bit instruction format (0 to 11 bit) are:
Addressing Mode (15th bit)
OPCODE (12, 13, 14 bit)
Operand Address
Step 4: Decode Phase occurring at Clock Pulse (T-2)
The CPU’s control unit decodes the program instruction once it is loaded into the instruction register (IR). A Decode Phase is the second phase of the instruction cycle.
The instruction is decoded by the CPU’s control unit based on the operation code (OPCODE), determined by three bits (bit 12, 13, 14).
Step 5: Decode Instruction Type occurring at Clock Pulse (T-2)
The CPU’s control unit must first decode the type of instruction. The three types of education are:
Memory reference instruction
Register reference instruction
Input/output instruction.
The 3 X 8 decoder determines the type of instruction. The D7 value determines the type of instruction. The three-bit OPCODE can have eight distinct values, starting with (DO, D1, D2, ….., D6, D7). Alternatively, the OPCODE can have values ranging from DO – 000 to D7 111.
Step 6: Decode Addressing Mode occurring at Clock Pulse (T-3)
If D7 is set to zero, the instruction type is a memory reference. When D7 is set to 1, the instruction type can be a register reference type or an input/output instruction. The instruction type is register reference type if D7 equals one and I equals 0. If D7 and I are both 1, the instruction type is input/output.
After deciding on the type of instructions and making a subsequent decision, the decode phase concludes. The value of I in the 15th bit determines the decode phase.
Technicalities involved in Indirect Cycle
After fetching an instruction, the next step involves fetching source operands. You can retrieve the source operand by using indirect addressing. However, you are free to bring it employing any addressing modes. There is no need to bring the register-based operands. Still, you may require to store the result in the main memory following the execution of the opcode.
The following micro-operations are carried out:
Step 1: The instruction cycle transfers the instruction’s address field to the MAR. It leads to obtaining the operand’s address.
Step 2: Through the process of direct addressing, the IR’s address field is updated from the MBR.
Step 3: The current state of IR through the direct addressing mode would have been different if indirect addressing had occurred.
However, note that the IR is now in a preparation stage for the execution cycle, but it skips it for a moment to consider the Interrupt Cycle.
Conclusion
This article covers various aspects of instructions fetch and decode. Depending on the program logic and algorithm, a computer program employs various types of program instructions. The program instruction, for example, can perform input and output operations, arithmetic calculations, or logical decision-making.