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Part 5- K map continued
Lesson 8 of 53 • 2 upvotes • 10:26mins
Abinaya Inbamani
GATE solved answers on k map
Digital Circuits: GATE (EEE)
53 lessons • 9h
1
Part 1-Number Systems
15:00mins
2
Part 2 - Binary Codes
14:55mins
3
Boolean Algebra
14:45mins
4
Part 3 Continued - Boolean Algebra
10:49mins
5
Part 4-SOP and POS
12:15mins
6
K-map
14:42mins
7
K map continued 1
13:16mins
8
Part 5- K map continued
10:26mins
9
Quine Mc cluskey algorithm for finding the minimal SOP
14:19mins
10
Logic gates along with GATE questions
11:54mins
11
IC digtial logic families
14:00mins
12
Special characteristics of IC Digital logic families
12:17mins
13
NAND NOR implementation
9:44mins
14
Adders and subtractors
14:22mins
15
Full subtractor , parallel adders and parallel subtractors
11:25mins
16
Multiplexers and demultiplexers
12:50mins
17
Encoders and decoders
8:38mins
18
Important questions related to digital logic circuits
9:06mins
19
GATE solved answers
9:20mins
20
Code converters
9:31mins
21
Latches
14:40mins
22
SR flip flop and D flip flop
8:35mins
23
Latches( JK flip flop and T flip flop)
9:59mins
24
Realisation of one flip flop using another flip flop
11:30mins
25
Realisation of one flip flop using another flip flop(continued)
9:14mins
26
Minterms and Maxterms
10:23mins
27
Solved GATE questions
9:40mins
28
Solved GATE questions
9:31mins
29
Solved GATE questions
6:35mins
30
Mod 6 counter
8:45mins
31
Master slave JK flip flop
7:02mins
32
Code converters
11:14mins
33
Design of a counter
8:35mins
34
Solved GATE questions
10:16mins
35
Classification of memories
9:09mins
36
Types of ROM (continued)
8:00mins
37
Random Access Memory
7:56mins
38
Types of ROM
12:43mins
39
Read only memory
9:24mins
40
Field Programmable Gate Array
7:22mins
41
BCD to gray code PLA
6:53mins
42
BCD to gray code PLA
6:53mins
42
Solved GATE questions
7:44mins
43
BCD to gray code PLA
6:53mins
43
Various Approaches of VHDL
11:22mins
44
Programmable Array Logic
7:18mins
45
Programmable Logic Array
8:19mins
46
Solved problems on PAL
6:51mins
47
Various Approaches of VHDL
11:22mins
47
Solved problems on PLA
7:44mins
48
Johnson counter
8:04mins
49
Universal shift registers
9:36mins
50
Ring counter
6:54mins
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