VLSI Technology

This course is an overview of Digital Design with Verilog HD: typical HDL-flow, why Verilog HDL, Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block etc.

GATE (Graduate Aptitude Test in Engineering) 2020 & 2021 complete preparation with best educators. Know about the detailed syllabus, best books, exam pattern and dates, previous year question papers a

GATE Iconic Pro

English

Verilog HDL

Advanced Electronics

GATE & ESE - EE, EC

GATE, ESE and IIT-JAM

Logical operators, relational operators, equality operators

Operators (part 2)

Overview of Verilog HDL

Hierarchical Modeling

Basic Concepts

Basic Concepts (Continuation)

Ports and Connections

Gate Level Modelling

Operators

Operators (part 3)

Dataflow Modeling

Dataflow Modeling (part 2)

Please Login To Continue

Operators (part 2)

Neha Singh

Verilog HDL

1

2

3

4

5

6

7

8

9

10

11

Crack GATE Iconic Pro with Unacademy

Get subscription and access unlimited live and recorded courses from India's best educators

Structured syllabus

Daily live classes

Ask doubts

Tests & practice

Similar Plus Courses

Phoenix All Star Fastrack Course on Physics for NEET 2025

Anubhav Shrivastava

Complete Course on Emerging Areas - NET/SET/GATE & Clinical Psychology

Hafsa Malik

Course on CSAT - Completely Based on New Pattern (Final Batch for 2025)

Madhukar Kotawe