Neha Singh

This course is an overview of Digital Design with Verilog HD: typical HDL-flow, why Verilog HDL, Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block etc.

GATE (Graduate Aptitude Test in Engineering) 2020 & 2021 complete preparation with best educators. Know about the detailed syllabus, best books, exam pattern and dates, previous year question papers a

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English

Verilog HDL

VLSI Technology

Advanced Electronics

GATE & ESE - EE, EC

GATE, ESE and IIT-JAM

Ace the toughest competitive and government exams in India 

Test Preparation

This video is an overview of digital design with verilog.
Emergence of HDLs, typical design flow, importance and features of HDLs are discussed along with the trends in HDLs

Overview of Verilog HDL

Hierarchical modelling concepts. In this video we discuss the two design methodologies. We understand what are modules and instances. Also we see the components required for stimulation.

Hierarchical Modeling

Basic Concepts

Continuation of basic concepts and system tasks

Basic Concepts (Continuation)

Components of a verilog module, ports and port connection rules

Ports and Connections

Gate-level modelling with examples of 4to1 mux and 4-bit ripple carry adder.
Gate delays: rise, fall and turn-off

Gate Level Modelling

Operators

Logical operators, relational operators, equality operators

Operators (part 2)

Bitwise operator, reduction operator, shift operators

Operators (part 3)

Operators and data flow Modeling introduction

Dataflow Modeling

Delays, designing 4-to-1 mux and 4-bit ripple carry full adder using dataflow Modeling

Dataflow Modeling (part 2)

electronics and communication engineer
pursuing M.Tech in vlsi technology


Ritika Chaudhary

this course deal with engineering student of electronics and communication background or vlsi technology background

(Hindi) Advanced vlsi Design

Research Assistant at Electronic Systems Engineering, Indian Institute of Science (IISc), Bangalore, GATE Qualified

Rudrarup Sengupta

This course in English and will guide you to understand the basics of IC fabrication required for GATE (EC). Only the required points are mentioned in interactive slides set with real-life examples.

IC Fabrication Technology and Processes

I'm an M.E graduate in embedded systems and technologies.  Cleared NET examination  in electronic science conducted by CBSE-UGC.

Niranjani S

This course deals with verilog coding techniques/types.

Verilog Coding

I am an EC Engineer of 3rd year.
I am a performer not a perfectionist.
Music,Writing are my loves.



Susmitha Kotakonda

This course gives detailed information about MOS transistors and their working, Modes of operation, MOS device design equations and their behaviour in various effects.

MOS Transistor Theory

I am pursuing  B.Tech in ECE. I like teaching .I hope my lessons will be beneficial for BTech students.

Shifali Srivastava

In this course, Shifali shall be discussing FSM types and examples. The course is for B Tech Students

Finite State Machine for B Tech Students

I have completed M.Tech in E&TC ( Signal Processing) and currently pursuing Ph.D.at Pune University. I have qualified GATE 2013.I have teach

Sarang Joshi

FIR filter design using windows , Frequency sampling , IIR filter design , implementation of Digital filters

Lessons

11 lessons • 2h 14m

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Overview of Verilog HDL

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Hierarchical Modeling

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Basic Concepts

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Basic Concepts (Continuation)

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Ports and Connections

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Gate Level Modelling

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Operators

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Operators (part 2)

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Operators (part 3)

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Dataflow Modeling

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