SR Latch Using NAND Gate and SR Flip Flop (in Hindi)

Lesson 4 of 7 • 4 upvotes • 14:50mins

Ankita Bhaskar

Operation, truth table, characteristic table and excitation table for SR flip flop. In SR flip flop when S = 1 and R = 1, it is considered as an invalid state because Qn and Qn* are not obtained as compliment states. Both outputs appear to be at the same logic which cannot be true.