Research enthusiast | writer | M.tech in Electronics | Motivator. 

Ankita Bhaskar

In this we are discussing brief about latch and flip flop which required for GATE

GATE (Graduate Aptitude Test in Engineering) 2020 & 2021 complete preparation with best educators. Know about the detailed syllabus, best books, exam pattern and dates, previous year question papers a

GATE - Iconic Pro

Hindi

(Hindi) Flip -Flop for GATE EC

Combinational Circuits

Digital Electronics

GATE & ESE - EE, EC

GATE, ESE and IIT-JAM

Ace the toughest competitive and government exams in India 

Test Preparation

Description of the course - "flip flops". Topics, objective and the people who can get benefit from this course is discussed here.

Overview (in Hindi)

Flip flops store 1 bit of information present at Qn output while Qn* is used to check if the FF is working properly. All important points regarding FF are provided in this lesson.

Flip Flop Basics (in Hindi)

Detailed description of latch using NOR gate is provided here. Latch can be made using any of the universal gates ( NAND & NOR)

Latch using NOR Gate (in Hindi)

Operation, truth table, characteristic table and excitation table for SR flip flop. In SR flip flop when S = 1 and R = 1, it is considered as an invalid state because Qn and Qn*  are not obtained as compliment states. Both outputs appear to be at the same logic which cannot be true.

SR Latch Using NAND Gate and SR Flip Flop (in Hindi)

Operation,truth table,characteristic table and excitation table for JK flip flop. JK flip flop is a modification of SR flip flop. The benefit of JK flip flop is that it makes the J = 1 and K = 1 as the valid state where toggling happens. While in the SR FF it is the invalid case.

JK Flip Flop (in Hindi)

Operation,truth table,characteristic table and excitation table for D flip flop. D stands for 'data' or 'delay'. Its output is same as that of the input. It is used to provide delay in a circuitry.

D Flip Flop (in Hindi)

Operation,truth table,characteristic table and excitation table of T flip flop. It is known as toggle flip flop and it provides only the toggling action in a controlled manner. It is made using JK flip flop.
Flip flops in general are interchangeable by making minute changes.

T Flip Flop (in Hindi)

Ex Deputy Engineer ( BEL ) , GATE Qualified, YouTuber (10x preparation) , Motivational speaker , Mentor

Kartik Bhardwaj

This course covers Sequential Circuits, specially designed for competitive exams like GATE/ESE /PSU.

(Hindi) Sequential Circuits for GATE Examination: Part 3

I am currently pursuing bachelor of engineering in electronics and telecommunication branch and I am a gate aspirants too.

Jyoti Prasad

It is all about asynchronous and synchronous counters,which we will deal in this course.

Counters for GATE

(Hindi) Sequential Circuits for GATE Examination: Part 2

M.Tech (Digital Communication) from IIIT-Gwalior, qualified GATE. Passionate for teaching. 

Sourabh Jain

In this course the Sequential circuits with all the important topics is covered along with problems of previous years of GATE,IES and PSUs.

(Hindi) Sequential Circuits for GATE (ECE)

B.E in Electronics & Communication, UPSC Aspirant , Love to teach , Bike Riding , Badminton ,Guitar ,cooking ,trekking ,Automation Projects.

Mohit Singh

This course covers the circuits used in combinational logic like adder, subtractor, magnitude comparator, arithmetic and non arithmetic circuits.

(Hindi) Combination Logic Circuits

 AIR 493 in GATE (ECE) & 2300+Students have been trained so far for GATE

Sreenivas Bhaskara

This Course is about Digital Circuits. 

This Course is beneficial for 
GATE (ECE)
 aspirants.

Lessons

7 lessons • 1h 18m

Invalid Date

NaN

Overview (in Hindi)

Invalid Date

NaN

Flip Flop Basics (in Hindi)

Invalid Date

NaN

Latch using NOR Gate (in Hindi)

Invalid Date

NaN

SR Latch Using NAND Gate and SR Flip Flop (in Hindi)

Invalid Date

NaN

JK Flip Flop (in Hindi)

Invalid Date

NaN

D Flip Flop (in Hindi)

Invalid Date

NaN

T Flip Flop (in Hindi)