Lesson 4 of 13 • 89 upvotes • 8:41mins
The output of the below multiplexer circuit can be represented by 1.AB+BC'+C'A+B'C'' 2.A⊕B⊕C 3.A⊕B 4.A'B'C+A'BC'+AB'C'
13 lessons • 1h 43m
Overview of the Course (in Hindi)
6:12mins
Multiplexer Selection Lines (in Hindi)
9:22mins
4-to-1 Multiplexer Solution (in Hindi )
8:55mins
Output of Multiplexer (in Hindi )
8:41mins
The Output of a 2:1 Mux (in Hindi )
8:19mins
Input NOR gate using two 2−4 MUX (in Hindi)
9:11mins
A two-input AND gate using two 2-1 multiplexers(in Hindi)
8:19mins
Two cascaded 2-to-1 multiplexers find minimal SOP (in Hindi)
7:26mins
Binary half adder output and sum values (in Hindi )
8:04mins
Logic function implemented by the circuit (ground “0”) (in Hindi)
8:05mins
The logic realized by the circuit shown in figure (in Hindi )
7:40mins
, I0 – I3 are input to the 4:1 multiplexer R (MSB) and S are control bits(in Hindi)
8:04mins
A circuit which is used to sent data from many to one( in Hindi )
5:21mins