ELECTRICAL ENGINEERING Gate 2018 Solutions
Presented by: Sanjeev Kumar https://unacademy.com/user /sanjeev.kumar92ex-8099
Exam Paltesn ection Lo (neutral Aph Judi T L to 5 [Lmarks 6 do lo L markes ecin TT[55 Scanned by CamScanner
In the logic circuit shown in the figure, Y is given by (A) Y = ABCD (C) Y=A+B+C+D (B) Y- (A + B)(C + D) (D) Y- AB + CD
A B Sudh Ta ble (WAwd) 010 Scanned by CamScanner
BE (electrical and electronics engineering) , Two times gate qualified (2017, 2018),Two years of teaching experience.