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Asynchronous DOWN Counter
Lesson 18 of 33 • 23 upvotes • 9:46mins
Jigyasa Singh
*Correction- In method-III, flip flops will trigger at negative going edge of clock (pulse going from high to low). Kindly correct the timing diagram accordingly.
(Hindi) Registers and Counters for GATE
33 lessons • 5h 39m
1
Introduction (in Hindi)
11:37mins
2
Classification of Shift Registers (in Hindi)
9:36mins
3
Shift Right SISO (in Hindi)
10:20mins
4
Shift Left SISO (in Hindi)
8:51mins
5
SIPO Register (in Hindi)
10:14mins
6
PISO Register (in Hindi)
11:24mins
7
PIPO Register
10:02mins
8
Buffer Register
10:11mins
9
Bidirectional Shift Register
7:32mins
10
Universal Register
11:23mins
11
Basics of Counters
11:14mins
12
Introduction to Counters
8:31mins
13
Ripple Counter (Mod-4 counter)
12:16mins
14
Mod-8 Counter
11:00mins
15
Mod-16 Counter
10:15mins
16
2-bit Up/Down Counter
9:45mins
17
3-bit Up/Down Counter
8:51mins
18
Asynchronous DOWN Counter
9:46mins
19
Divide-by-N Ripple Counter
8:14mins
20
BCD Counter/Decade Counter
10:49mins
21
2-bit Synchronous Counter
12:01mins
22
3-bit Synchronous Counter
9:11mins
23
Modulus-N Synchronous Counter
13:05mins
24
Up/Down Synchronous Counter
12:51mins
25
Lockout Condition
12:24mins
26
Ring Counter
12:02mins
27
Johnson Counter/ Twisted ring Counter
10:44mins
28
Gate Question (1992-1994)
8:26mins
29
Gate Question (1995-1998)
11:39mins
30
Preset & Clear S/g + Gate Question (1999)
8:49mins
31
Gate Question (2000)
6:25mins
32
Gate Question (2002-2003)
8:48mins
33
Gate Question (2004)
10:57mins
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