Xilinx : Introduction to Design

Xilinx : Role of Programmable Logic and FPGA

Xilinx : Design Tools

Xilinx Case Study : System Design

Xilinx : Applications

Introduction to VLSI Design: Brief History

FPGA Devices

Learning Installing Xylinx

Downloading and installing XILINX VIVADO tool

Creating Timing Constraints

Geting started with Vivado IDE - II

Basics of Digital Circuit Design - II

Digital Design Using Verilog HDL

Examples to Understand Basic Concepts of Verilog :I

Examples to Understand Basic Concepts of Verilog : II

Introduction - Gate Level Modeling

Live Coding on Gate level Modeling

Project: Four Bit Ripple Carry Adder

Types of modeling in Verilog

Data Flow Modeling & Types of Operators

Project: Data Flow Modeling - I

Project: Data flow Modeling - II

Behavioral Modeling: Introduction

Blocking and Non-blocking Assignments

Timing Control & Related Project - I

Timing Control & Related Project - II

Conditional Statement, Branching & Loops

Loops, Sequential, and Parallel Blocks

Non Synthesizable Delay & Programming

Switch - Level Modeling with Examples

User-defined primitives (UDPs) in verilog

Tasks & Functions

FPGA Architecture Overview

FPGA Slices, LUTs, and Registers

FPGA Implementation Using LUTs, Flip-Flops, and Carrychain

Propagate (P) and Generate (G)

Basic Introduction of Static Timing Analysis (STA)

Setup Time, Hold Time, & Slack

Design constraints

STA Using Xilinx Vivado

Xilinx Vivado IP

Xilinx Vivado ILA IP

Creating an HDL Source

XYLINX- ISE

Software & Tools

Post Graduate Program in Electrical and Electronics Engineering

Others

Ace the toughest competitive and government exams in India 

Test Preparation

English

All questions

XILINX VIVADO

XYLINX- ISE

Chapters

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Learning Installing Xylinx

Creating Timing Constraints

Practice

Creating an HDL Source