A 3rd year engineering student of Electronics And Communication Engineering (ECE)branch, from University Institute Of Engineering And Techno

Mehul Garg

In this course, different levels of modelling are explained from the very basic. The first one is gate level modelling with various gate circuits

GATE (Graduate Aptitude Test in Engineering) 2020 & 2021 complete preparation with best educators. Know about the detailed syllabus, best books, exam pattern and dates, previous year question papers a

GATE - Iconic Pro

English

Modelling In Verilog

VLSI Technology

Advanced Electronics

GATE & ESE - EE, EC

GATE, ESE and IIT-JAM

Ace the toughest competitive and government exams in India 

Test Preparation

Introduction to Operators

Types of Operators part 2

Details about what I module, gate level modelling with example

Gate Level Modelling

Multiplexer 4:1 and full adder using gate level modelling

4:1 Multiplexer and Full Adder using Gate Level Modelling

Different types of gate delays with examples

Gate Delays

electronics and communication engineer
pursuing M.Tech in vlsi technology


Ritika Chaudhary

this course deal with engineering student of electronics and communication background or vlsi technology background

(Hindi) Advanced vlsi Design

Research Assistant at Electronic Systems Engineering, Indian Institute of Science (IISc), Bangalore, GATE Qualified

Rudrarup Sengupta

This course in English and will guide you to understand the basics of IC fabrication required for GATE (EC). Only the required points are mentioned in interactive slides set with real-life examples.

IC Fabrication Technology and Processes

I'm an M.E graduate in embedded systems and technologies.  Cleared NET examination  in electronic science conducted by CBSE-UGC.

Niranjani S

This course deals with verilog coding techniques/types.

Verilog Coding

Neha Singh

This course is an overview of Digital Design with Verilog HD: typical HDL-flow, why Verilog HDL, Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block etc.

Verilog HDL

I am an EC Engineer of 3rd year.
I am a performer not a perfectionist.
Music,Writing are my loves.



Susmitha Kotakonda

This course gives detailed information about MOS transistors and their working, Modes of operation, MOS device design equations and their behaviour in various effects.

MOS Transistor Theory

I have completed M.Tech in E&TC ( Signal Processing) and currently pursuing Ph.D.at Pune University. I have qualified GATE 2013.I have teach

Sarang Joshi

FIR filter design using windows , Frequency sampling , IIR filter design , implementation of Digital filters

Lessons

5 lessons • 1h 13m

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Introduction to Operators

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Types of Operators part 2

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Gate Level Modelling

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4:1 Multiplexer and Full Adder using Gate Level Modelling

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Gate Delays