Research Assistant at Electronic Systems Engineering, Indian Institute of Science (IISc), Bangalore, GATE Qualified

Rudrarup Sengupta

This course in English and will guide you to understand the basics of IC fabrication required for GATE (EC). Only the required points are mentioned in interactive slides set with real-life examples.

GATE (Graduate Aptitude Test in Engineering) 2020 & 2021 complete preparation with best educators. Know about the detailed syllabus, best books, exam pattern and dates, previous year question papers a

GATE & ESE

English

IC Fabrication Technology and Processes

VLSI Technology

Advanced Electronics

GATE & ESE - EE, EC

GATE, ESE and IIT-JAM

Ace the toughest competitive and government exams in India 

Test Preparation

IC Fabrication Process - 1

IC Fabrication Process - 2

IC Fabrication Process - 3

IC Fabrication Process - 4

IC Fabrication Process - 5

IC Fabrication Process - 6

IC Fabrication Process - 7

IC Fabrication Process - 8

IC Fabrication Process - 9

IC Fabrication Process - 10

IC Fabrication Process - 11

IC Fabrication Process - 12

IC Fabrication GATE Questions - 1 (2003-2010)

IC Fabrication GATE Questions - 2 (2010-2018)

Pursuing B.tech in Electrical and Electronics Engineering,NIT Tiruchirappalli. Computer Science enthusiast and an optimist.

Sanjana Pedada

This course will discuss the basic steps of IC Fabrication and Fabrication of NMOS and CMOS inverter ( N- well and Twin Tub process)

VLSI Process Technology: GATE

electronics and communication engineer
pursuing M.Tech in vlsi technology


Ritika Chaudhary

this course deal with engineering student of electronics and communication background or vlsi technology background

(Hindi) Advanced vlsi Design

I'm an M.E graduate in embedded systems and technologies.  Cleared NET examination  in electronic science conducted by CBSE-UGC.

Niranjani S

This course deals with verilog coding techniques/types.

Verilog Coding

Neha Singh

This course is an overview of Digital Design with Verilog HD: typical HDL-flow, why Verilog HDL, Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block etc.

Verilog HDL

I am an EC Engineer of 3rd year.
I am a performer not a perfectionist.
Music,Writing are my loves.



Susmitha Kotakonda

This course gives detailed information about MOS transistors and their working, Modes of operation, MOS device design equations and their behaviour in various effects.

MOS Transistor Theory

I have completed M.Tech in E&TC ( Signal Processing) and currently pursuing Ph.D.at Pune University. I have qualified GATE 2013.I have teach

Sarang Joshi

FIR filter design using windows , Frequency sampling , IIR filter design , implementation of Digital filters

Lessons

14 lessons • 2h 30m